Download Advanced Parallel Processing Technologies: 9th International by Kunal Korgaonkar, Prabhat Jain, Deepak Tomar (auth.), PDF

By Kunal Korgaonkar, Prabhat Jain, Deepak Tomar (auth.), Olivier Temam, Pen-Chung Yew, Binyu Zang (eds.)

This ebook constitutes the refereed complaints of the ninth overseas Symposium on complicated Parallel Processing applied sciences, APPT 2011, held in Shanghai, China, in September 2011.

The thirteen revised complete papers provided have been conscientiously reviewed and chosen from forty submissions.
The papers are equipped in topical sections on parallel dispensed procedure architectures, structure, parallel software and software program, allotted and cloud computing.

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Extra info for Advanced Parallel Processing Technologies: 9th International Symposium, APPT 2011, Shanghai, China, September 26-27, 2011. Proceedings

Example text

Qureshi et al. [10] adopted a smaller DRAM acting as a cache for a large PCM main memory. Qureshi et al. [24] proposed adaptive Write Cancelation policies combined with Write Pausing policies to improve read performance. Wu[23] et al. proposed read-write aware Hybrid Cache Architecture, where a single level cache can be partitioned into read region (SRAM ) and write region (PCM or MRAM). Then cache line migration policy is proposed to move data between regions. However the policy is only fit for its specific organization and requires extra hardware overhead and instruction extension.

Phase-change random access memory: A scalable technology. IBM Journal of R. and D. 52(4/5), 465–479 (2008) 6. html 7. Intel. Intel, STMicroelectronics Deliver Industry’s First Phase Change Memory Prototypes. Intel News Release (February 6, 2008) 8. : Hybrid cache architecture with disparate memory technologies. In: ISCA 2009, pp. 34–45 (2009) 9. : Two-bit Cell Operation in Diode-Switch Phase Change Memory Cells with 90nm Technology. In: IEEE Symposium on VLSI Technology Digest of Technical Papers, pp.

In summary, these capabilities combined with low memory cost makes PCM a promising candidate for main memory, though there are some disadvantages to overcome. In next section, we propose a method to reduce write penalty incurred by PCM. 3 Read-Write Aware Replacement Policy In this section, we first describe overview of RWA. Then our proposed ReadWrite Aware policy and its improved version are illustrated in details. 1 Overview Fig. 2 shows two systems in which PCM acts as main memory. g. MacBook FLASH-BASED SSD FLASH-BASED SSD PCM PCM DRAM P1 Pn (a) Pn P1 (b) Fig.

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